1. Technical Field
The present invention relates generally to a semiconductor integrated circuit, and more particularly, to a mechanism that changes the frequency of a clock in a semiconductor apparatus.
2. Related Art
In general, a semiconductor apparatus performs a read is operation or a write operation by synchronizing a command with the edge of a clock.
For example, a semiconductor apparatus synchronizes a command with the rising edge of a clock and provides the command to an internal circuit. The command should be provided a predetermined time before the arrival of the rising edge of the clock, to ensure that the semiconductor apparatus is in a standby state to precisely recognize and receive the command at the rising edge of the clock. Also, the level of the command should be retained for a predetermined time even after the rising edge of the clock, to ensure that the semiconductor apparatus precisely performs the mode indicated by the command.
The predetermined time by which a command should be provided before the arrival of the edge of a clock for synchronization is referred to as setup time, and the predetermined time by which the level of the command should be retained is referred to as hold time.
FIG. 1 is a block diagram of the command latch unit of a conventional semiconductor apparatus. The command latch unit of the semiconductor apparatus includes a latch section 10 which receives a command CMDB and outputs an internal command ICMD in synchronization with a clock CLK. The command CMDB may be a plurality of commands, such as a chip select signal CS, an active signal ACT, a row address strobe signal RAS, a column address strobe signal CAS and a write enable signal WE. Accordingly, the command latch unit of the semiconductor apparatus may be constituted by a plurality of latch sections to latch the respective commands.
FIGS. 2a and 2b are timing diagrams of the command latch unit of the conventional semiconductor apparatus.
Generally, the read or write operation of the semiconductor apparatus is performed by combining the plurality of commands CMDB such as the chip select signal CS, the active signal ACT, the row address strobe signal RAS, the column address strobe signal CAS, the write enable signal WE, and so on. Thus, if the pulse width of the command CMDB is the same as one cycle (1*tCK) of the clock CLK as shown in FIG. 2a, the internal command ICMD has the same setup/hold time as the pulse width of the command CMDB, and the semiconductor apparatus may precisely perform the mode indicated by the command CMDB.
However, if the pulse width of the command CMDB is larger than one cycle (1*tCK) of the clock CLK as shown in FIG. 2b, the internal command ICMD has a different setup/hold time from the pulse width of the command CMDB, and the semiconductor apparatus may not precisely recognize the mode indicated by the command CMDB. In the case where the pulse width of the internal command ICMD changes, the semiconductor apparatus may fail to perform an operation mode according to an input signal.